Bit serial encoder
US4410989A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 1980 |
| Grant date | Oct 18, 1983 |
| Priority date | — |
| Expiry date | Dec 11, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An encoder for Reed Solomon codes employs structure for producing interleaved code wherein redundancy bits are realized by a bit serial multiplicative procedure. Operations are accomplished with respect to the dual basis to the conventional polynomial representational basis as coefficients of successive powers of an element of a finite field. Code bits are generated and interleaved by a feedback shift register constructed from standard RAM chips. The structure is simplified by selection of a generator polynomial from a class which exhibits symmetry whereby the number of independent coefficients for representing the generator polynomial is halved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.