Process for fabricating CMOS devices with self-aligned channel stops
US4411058A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1981 |
| Grant date | Oct 25, 1983 |
| Priority date | — |
| Expiry date | Aug 31, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
Abstract
An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type conductivity, respectively. Conventional source, drain and gate portions are formed in the regions and electrical contacts are made thereto. The improvement comprises providing self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity. The channel stops between regions of the opposite conductivity are mutually self-aligned. The self-alignment is achieved by use of a single mask, called a "complementary" mask. The process of the invention permits fabrication of submicrometer devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.