Random access memory system having high-speed serial data paths
US4412313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1981 |
| Grant date | Oct 25, 1983 |
| Priority date | — |
| Expiry date | Jan 19, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To substantially increase the bandwidth of a random access memory (RAM), a shift register is disposed within the memory array such that the shift register lies parallel to the word lines and is connected to at least individual ones of the bit lines contained within the array. Separate high-speed serial input and output lines are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.