Clock synchronization system
US4412342A · kind A · utility
25Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1981 |
| Grant date | Oct 25, 1983 |
| Priority date | — |
| Expiry date | Dec 18, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock synchronization system for use in a digital switching system including multiple clock circuits. This circuit includes multiple synchronization circuits connected in a master-slave arrangement. Each synchronization circuit includes a counter chain which provides a periodic system framing pulse and a trigger circuit which insures that its slave system framing pulse is in synchronization with the master system framing pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.