Self-testing pipeline processors
US4414669A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1981 |
| Grant date | Nov 8, 1983 |
| Priority date | — |
| Expiry date | Jul 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to pipeline processors having testing means for identifying malfunctioning modules and for testing the self-testing means themselves. The testing employs the parity check principle and provides an on-line test of memory modules and an off-line test at the processor clock rate of both memory and arithmetic modules. The means for testing include a parity encoder associated with each module and a comparator which couples parity "comparison values" to a priority encoder, operating at the high speed clock rate of the pipeline processor. The test results are then supplied to a RAM, also operating at the clock rate of the pipeline processor. With the test results in the memory, a microcomputer is provided to search the memory at a slower rate for the highest priority failed module. Means are also provided for parity checking the testing means such as the test vector generator, as well as the pipeline processor
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.