Cache/disk subsystem with load equalization
US4415970A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1980 |
| Grant date | Nov 15, 1983 |
| Priority date | — |
| Expiry date | Nov 14, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system wherein processors are connected through channel units to disk devices, two storage control units (SCU's) are provided between the channel units and the disk devices. The SCU's receive commands from the processor and issue seek instructions to the devices to locate the disk space specified by the commands, provided that a copy of the data from the specified disk space is not resident in a cache store. The commands may be queued for a time in a memory which is accessible by both SCU's. Before issuing a seek instruction to a device, an SCU first determines whether it is the only SCU having a path through a channel unit back to the processor which issued the command or whether there is a path from each SCU to the processor. If both SCU's have a path back to the processor, the SCU issues an untagged seek instruction to the device. If not, the SCU issues a tagged seek instruction to the device. When the disk device completes a seek resulting from a tagged instruction, it sends an interrupt to the SCU which issued the seek and that SCU then notifies the processor which issued the command. In response to the notification the processor issues the command a second time and it is…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.