Synchronous clock regenerator for binary serial data signals
US4415984A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1980 |
| Grant date | Nov 15, 1983 |
| Priority date | — |
| Expiry date | Jun 25, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit. Thereafter, and until the next framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the l-of-n selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.