Clock generator circuit
US4417158A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Nov 18, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit for generating two pairs of clock signals comprises a NAND circuit and a NOR circuit cross-coupled to each other and each having an input for receiving a reference clock signal (.phi..sub.0). A first inverter is provided between the output of the NAND circuit and the other input of the NOR circuit, and a second inverter is provided between the output of the NOR circuit and the other input of the NAND circuit. A pair of clock signals (.phi..sub.2, .phi..sub.2) are generated from the NAND circuit and the first inverter, while another pair of clock signals (.phi..sub.1, .phi..sub.1) are generated from the NOR circuit and the second inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.