Power and ground plane structure for chip carrier
US4417266A · kind A · utility
186Cited by
2References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 14, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Aug 14, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to the chip carrier with the bus structure over a thermal pad formed within the bus structure. A decoupling capacitor is located in close proximity to the chip on the substrate to assure low reaction due to switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.