Multi-processor data communication bus structure
US4417303A · kind A · utility
17Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Feb 25, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus structure for the interconnection between a data bus capable of transferring a plurality of words and a local bus which can carry only one word. This structure includes latches for storing the plurality of words for simultaneous transfer over the data bus or for sequential transfer over the local bus as required. Control logic operates to perform the necessary control over this interconnection to effect the required operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.