Parallel operating mode arithmetic logic unit apparatus
US4417314A · kind A · utility
15Cited by
4References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Jul 14, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus is presented for logically combining two input signals in parallel operations to provide AND and OR as well as Exclusive OR outputs as part of the ALU function in a digital computer. The carry function is used in combination with the already generated signals of AND, OR and Exclusive OR to provide a carry output signal and a SUM signal through logic combining techniques. Thus, the entire ALU output is obtained in two stages of time delay and a great savings in components. In some computers, the outputs need to be passed through a four to one multiplexer to select the desired output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.