Method and apparatus for incrementing a digital word
US4417315A · kind A · utility
10Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Jul 14, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5055
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is presented designed specifically for use in complementary symmetry design techniques such as CMOS/SOS wherein inverting gate types are a preferred design. This design is obtained with a minimum of delay by changing gate types in the ripple carry path wherein alternating stages utilize NAND gates with the remaining ripple carry path stages using NOR gates. To accomplish this approach, the bit stages of the word utilizing the NOR gates must have the bits inverted before being applied to the incrementing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.