Adaptive analog processor
US4417317A · kind A · utility
19Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1982 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | Mar 5, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H21/0001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adaptive analog processor incorporating a analog shift register having a plurality of taps, multipliers at each tap for multiplying the tap value times a weight value, a first adder for summing the output of the multipliers, a second adder for subtracting the output of the adder from a second analog signal, means for incrementing the weights in response to the magnitude and polarity of the error signal and the polarity of the data signal. The invention overcomes the problem of building monolithic multitap adaptive filters utilizing the clipped-data least mean square error algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.