Interface for data communication systems using serial biphase data transmissions
US4417320A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 1981 |
| Grant date | Nov 22, 1983 |
| Priority date | — |
| Expiry date | May 11, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4904
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface for biphase data communication systems utilizing serial transmissions between a central control unit and a peripheral device. A ROM-latch network serving as a sequencer is utilized as a bi-directional biphase serial/TTL parallel translator. In the receiver mode the ROM-latch will step through a specific operational sequence for detecting an appropriate header and controlling a TTL parallel translation of the serial biphase data. In the transmitter mode the ROM-latch is used to reconstruct the header sequence prior to retranslating and transmitting the TTL parallel data in serial biphase format. A receiver clock generator circuit is provided for generating clock pulses for the ROM-latch in synchronism with the incoming biphase transmissions. A transmitter level converter defines the waveforms for the biphase data transmitted from the interface and is designed to provide a predistortion pulse at each voltage level transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.