Bias circuit for microwave FETs
US4419632A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 1981 |
| Grant date | Dec 6, 1983 |
| Priority date | — |
| Expiry date | Dec 11, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a circuit for biasing FETs which limits unwanted gate current. A first resistor (R.sub.8) is coupled in series with the gate and the output (14) of a differential amplifier (12). Means such as a second resistor (R.sub.9) and a Zener diode (D.sub.2) are coupled to the first resistor and one input of the differential amplifier. Means such as a third resistor (R.sub.3) is also coupled to one input of the amplifier. When excessive gate current appears, the voltage across the first resistor is such as to cause sufficient current flow through the diode and second and third resistors to unbalance the amplifier. This keeps the gate-to-source voltage of the FET at a region of gate current below some maximum value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.