Main bus interface package
US4419724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1980 |
| Grant date | Dec 6, 1983 |
| Priority date | — |
| Expiry date | Apr 14, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system having a plurality of units and a priority controller for controlling access to a bus by any of the units, each of the units is provided with a lock register having a stage corresponding to each unit connected to the bus. Each word placed on the bus by a source unit includes a lock bit which, in each unit except the source and destination units, sets the stages of the lock registers corresponding to the source and destination units. When a stage of a lock register is set it prevents the unit in which the register is located from attempting to communicate with a unit whose stage of the lock registers is set. On the last transmission between two units the word placed on the bus has a false lock bit which resets the stages of all of the lock registers corresponding to the source and destination units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.