Augmented phase-locked loop for very wide range acquisition and method therefor
US4419760A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1982 |
| Grant date | Dec 6, 1983 |
| Priority date | — |
| Expiry date | Jan 29, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An augmented phase-locked loop for use with a data communication system in which the data is encoded into a plurality of symbol signals such that the channel on which transmission occurs is switched at a data clock rate between symbol signals and such that two like symbol signals cannot appear successively. The coincidental transitions between symbol signals are detected and are used to lock a phase-locked loop. If the integrated signal from a transition detector is greater than integration of the signal level of the pluses on each incoming channel at the frequency of the loop locking to a subharmonic is detected and causes a sweep circuit to drive an oscillator to sweep until the phase-locked loop locks on the correct data clock frequency. The frequency to which the loop is locked is used to clock a successive sampling of each input so that if the loop is locked on a harmonic of the correct data clock, the sequential repetition of a symbol signal on a channel is detected and is used to force an oscillator to sweep until the phase-locked loop is locked to the correct data clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.