Formation of patterned film over semiconductor structure
US4420365A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 1983 |
| Grant date | Dec 13, 1983 |
| Priority date | — |
| Expiry date | Mar 14, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques of electroless metal deposition after first applying a mask which is positive with respect to the predetermined pattern. In alternative embodiments, the application to the masked protective layer of an agent catalytic to the reception of electroless metal deposition is followed by either immersion in an electroless plating bath and subsequent mask removal, or by mask removal and subsequent immersion in the electroless plating bath. In either embodiment, the protective layer is effectively masked and patterned for plasma etching. The process is useful in forming openings in the protective layer to permit selective doping of the underlying substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.