Method of controlling channel length by implanting through polycrystalline and single crystalline regions followed by diffusion anneal
US4420870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1981 |
| Grant date | Dec 20, 1983 |
| Priority date | — |
| Expiry date | Sep 23, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing semiconductor devices containing at least one MOS field effect transistor (FET) so as to control the effective channel length thereof and prevent channel-shortening. A mask wider than the desired MOS FET channel is formed on the surface of a first single-crystalline silicon semiconductor region, and the lattice structure of the unmasked surface portions thereof are randomized or disordered by silicon ion-implantation or by etching. After removal of the mask, epitaxial growth produces a polycrystalline region on the randomized regions and a second single-crystalline region on the previously masked region. An insulated gate electrode narrower than the single-crystalline region is formed centrally thereupon for serving as a mask during impurity implantation into the polycrystalline region and the portions of the second single-crystalline region adjacent thereto. In subsequent heat treatment impurity diffusion is slower in the second single-crystalline region that in the polycrystalline region, advantageously inhibiting lateral impurity diffusion from the second single-crystalline region into the channel underlying the gate electrode, thereby to control chann…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.