Binary MOS switched-carry parallel adder
US4422157A · kind A · utility
8Cited by
4References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1981 |
| Grant date | Dec 20, 1983 |
| Priority date | — |
| Expiry date | Aug 26, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast and inexpensive MOS switched carry parallel full adder is disclosed. Each stage includes only one inverter and two shunting transistors for the carry signal, one transistor being of the depletion type. Each stage further includes two EXCLUSIVE-OR gates and two NOR gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.