System for phase locking clock signals to a frequency encoded data stream
US4424497A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1981 |
| Grant date | Jan 3, 1984 |
| Priority date | — |
| Expiry date | Apr 30, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0993
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a system having a frequency encoded data stream and a source of clock signals phase locked to the data stream, for subsequent demodulation of the data stream, the clock source is at a frequency that is a multiple of the nominal frequency for demodulating, and a counter is employed to divide the clock. The counter is controlled by the output of a phase comparator, to control the addition to and inhibiting of counting of the counter. The control circuit controls the counter in a non-linear relationship with respect to the phase error, and has a memory function for storing previous states of the counter, to permit repetitive correction for small errors in the same manner. The phase comparator and control are preferably a programmed logic array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.