Odd/even bank structure for a cache memory
US4424561A · kind A · utility
39Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1980 |
| Grant date | Jan 3, 1984 |
| Priority date | — |
| Expiry date | Dec 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.