Memory cell resistor device
US4426655A · kind A · utility
3Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1981 |
| Grant date | Jan 17, 1984 |
| Priority date | — |
| Expiry date | Aug 14, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.