Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory
US4426681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1981 |
| Grant date | Jan 17, 1984 |
| Priority date | — |
| Expiry date | Jan 22, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes at least two processors, each having a cache memory containing an index section and a memory section. A first processor performs a task by deriving internal requests for its cache memory which also may respond to an external request derived from the other processor which is simultaneously processing a task. To avoid a conflict between the simultaneous processing of an internal request and of an external request by the same cache memory, one request may act on the other by delaying its enabling or by suspending its processing from the instant at which these requests are required to operate simultaneously on the index section or the memory section of the cache memory of the processor affected by these requests. Thereby, the tasks are performed by the system at an increased speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.