Method of fabricating high density high breakdown voltage CMOS devices
US4426766A · kind A · utility
9Cited by
11References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 21, 1981 |
| Grant date | Jan 24, 1984 |
| Priority date | — |
| Expiry date | Oct 21, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.