High density memory cell
US4427989A · kind A · utility
20Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1981 |
| Grant date | Jan 24, 1984 |
| Priority date | — |
| Expiry date | Aug 14, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.