High voltage on chip FET driver
US4429237A · kind A · utility
8Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1981 |
| Grant date | Jan 31, 1984 |
| Priority date | — |
| Expiry date | Mar 20, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High voltage tolerant FET circuits are characterized by the use of shield structures surrounding source/drain diffusion pockets, with the shields tied to apropriate potentials, which in some cases is the associated gate potential. Some embodiments use enhancement mode devices which however have implanted channels underlying the shield structures. Operation of several embodiments is achieved near the snap-back limits by the use of a clamp to maintain potential drop below this limit. High voltage switching at heavy loads is achieved by a voltage divider providing appropriate gate potentials to the load carrying FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.