Data buffer operating in response to computer halt signal
US4429362A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1981 |
| Grant date | Jan 31, 1984 |
| Priority date | — |
| Expiry date | Jun 18, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer can exchange data between a computer having a plurality of lines and a device. One of these lines, a halt line, can transmit a halt signal when the computer has halted. The buffer includes a plurality of transmitters and a plurality of controlled receivers. A halt transmitter is included among the plurality of transmitters. The transmitters are separately connected to predetermined respective ones of the plurality of lines for transmitting their signals to the device. The halt transmitter is connected to the halt line for transmitting the halt signal to the device. The receivers are connected between the device and given respective ones of the plurality of lines for coupling to them signals from the device. Each one of a predetermined set from the plurality of receivers has a receive terminal commonly connected to the halt line for enabling operation of this predetermined set in response to the halt signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.