Arithmetic unit for use in a data processing system for computing exponent results and detecting overflow and underflow conditions thereof
US4429370A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1981 |
| Grant date | Jan 31, 1984 |
| Priority date | — |
| Expiry date | Apr 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.