Consecutive addressing of a semiconductor memory
US4429375A · kind A · utility
30Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1981 |
| Grant date | Jan 31, 1984 |
| Priority date | — |
| Expiry date | Jul 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.