Memory interface system having combined command, address and data buss
US4430724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1980 |
| Grant date | Feb 7, 1984 |
| Priority date | — |
| Expiry date | Jun 26, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface system employs a communications protocol to distinguish between command signals, address signals and data signals appearing on the same bus lines. Each memory coupled to the bus lines detects the change between a default state on the bus lines and a command signal. A detector within each memory determines from the received command signal the type of memory operation to be performed and prepares the memory for that operation. These operations may include reading or writing data within specified locations in the memory or reading or writing within the program counter associated with the memory. The detector is only responsive to received command signals when a predetermined state follows the default state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.