Exclusive or circuit and parity checking circuit incorporating the same
US4430737A · kind A · utility
12Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1982 |
| Grant date | Feb 7, 1984 |
| Priority date | — |
| Expiry date | Jan 26, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/212
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.