Address generating apparatus and method
US4432053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1981 |
| Grant date | Feb 14, 1984 |
| Priority date | — |
| Expiry date | Jun 29, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range. Selective indexed addressing is employed for providing both index data and variable dimension override data. During address generation, selected index data is used in conjunction with a displacement provided by an instruction for determining an offset. Dimension override data accompanying the selected index data is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.