Sequential word aligned addressing apparatus
US4432055A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1981 |
| Grant date | Feb 14, 1984 |
| Priority date | — |
| Expiry date | Sep 29, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.