Multilevel metallization process for integrated circuits
US4436582A · kind A · utility
32Cited by
1References
6Claims
0Family size
Inventor
Key dates
| Filing date | Oct 28, 1980 |
| Grant date | Mar 13, 1984 |
| Priority date | — |
| Expiry date | Oct 28, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilevel metallization process which allows fabrication of several types of high density MOS and bipolar integrated circuits. The process uses a pad located under the inter-layer contact opening. The material of the pad is poly-silicon (doped or undoped), a refractory metal, or a refractory metal silicide which is not capable of being attacked during chemical etching of the metallization layers. If poly-silicon is used, it is either doped during its deposition or during contact doping, or it is automatically silicided during ohmic and Schottky contact formations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.