Feedback-controlled substrate bias generator
US4439692A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1981 |
| Grant date | Mar 27, 1984 |
| Priority date | — |
| Expiry date | Dec 7, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.