Page controlled cache directory addressing
US4441155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1981 |
| Grant date | Apr 3, 1984 |
| Priority date | — |
| Expiry date | Nov 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class addressing controls are modified to change the distribution of cache contained data more uniformly among the congruence classes in the cache (by comparison with conventional cache class distribution). The cache addressing controls change the congruence class address as a function of the state of a higher-order bit or field in any CPU requested address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.