Digital adder circuit for binary-coded numbers of radix other than a power of two
US4441159A · kind A · utility
6Cited by
10References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 7, 1981 |
| Grant date | Apr 3, 1984 |
| Priority date | — |
| Expiry date | Jul 7, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital adder circuit for binary-coded-decimal operation, comprising a set of multiplexers (11) which are conditioned with a pattern of input bits causing them to form an intermediate result (IR) equal to the sum of the two operands (A0-A3, B0-B3) plus a correction value of six. The intermediate result is adjusted by subtracting the correction value if the intermediate result is less than sixteen. The circuit is also operable in a pure binary mode, or can be made to perform various logical operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.