Repetitious logic state signal generation apparatus
US4441182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1981 |
| Grant date | Apr 3, 1984 |
| Priority date | — |
| Expiry date | May 15, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/322
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus as disclosed which comprises a register normally operable in the parallel data in/parallel data out mode but which has control mechanisms for allowing it to be converted to a serial data in/serial data out register. This register comprises part of a register based state machine. When the register is locked in a given mode so that a predefined control bit pattern is maintained within the register while the rest of the state machine operates in a normal manner, the control bit pattern is iteratively executed which in turn allows the use of an oscilloscope to observe signals in the signal transmission path of the state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.