Electrically programmable read-only memory stacked above a semiconductor substrate
US4442507A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1981 |
| Grant date | Apr 10, 1984 |
| Priority date | — |
| Expiry date | Feb 23, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the address decode means respectively couple through the insulating layer to the select lines. Each cell of the memory is comprised of a pair of the select lines and further includes a resistive means between that pair which irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross, and the resistance states are representative of the information in the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.