Storage cells for use in two conductor data column storage logic arrays
US4442508A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1981 |
| Grant date | Apr 10, 1984 |
| Priority date | — |
| Expiry date | Oct 16, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clocked storage logic array is formed from a plurality of columns and a plurality of rows disposed orthogonal to the columns. Logic cells interconnect selected columns and rows. Storage cells are operatively associated with some of the columns in the array, known as data columns. The storage cells utilize only two column conductors which are time shared to provide a data path from a memory element in the storage cell to a specified row or rows and back from the row(s) through the same column conductors to the memory. A plurality of phase-displaced clock periods are generated which operate in association with the storage cells to enable the two column conductors to be time shared. The clock periods also cooperate with logic cells to cause selected rows to assume binary states determined by the binary state of interconnected columns, and vice-versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.