Semiconductor memory byte clear circuit
US4442510A · kind A · utility
2Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1981 |
| Grant date | Apr 10, 1984 |
| Priority date | — |
| Expiry date | Dec 28, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.