Memory address sequence generator
US4442519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1982 |
| Grant date | Apr 10, 1984 |
| Priority date | — |
| Expiry date | Mar 5, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Apparatus consisting of combinations of interconnected logic elements for generating preselected sequences of addresses for the listing of a matrix memory as a function of preset constants and variable timing impulses, wherein there are first and second X and Y address generators with controlled selection means for selecting the first or the second of the X and Y address pairs, each of the address generators being settably controllable to generate a preselected sequence of addresses in ascending or descending order, with settable increments within the sequence, settable masking, and settable displacements from a fixed reference origin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.