Memory system having a common interface
US4443845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1980 |
| Grant date | Apr 17, 1984 |
| Priority date | — |
| Expiry date | Jun 26, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having separate read-only memory and read-write memory integrated circuits coupled to a central processing unit via the same interface system. The data processing system is comprised of bus means having either command, address, or data signals present and conducted thereon. In the preferred embodiment, the bus means is comprised of a four binary digit bidirectional conductor bus coupling between the central processing circuit and the memory circuits. In the preferred embodiment, the data processing system is further comprised of processor means within said central processing unit coupled to the bus means for selectively transmitting selected ones of said command, data and address signals onto the bus means, said processor means further including means for receiving certain other ones of said data and address signals from the bus means; and memory means including, in the preferred embodiment, read-only memory circuits and read write memory circuits, coupled to the bus means (and to the processor means via the bus means), including means for selectively transferring data with the processor means in response to said received command and address signals being w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.