Method of fabricating a semiconductor device with a base region having a deep portion
US4443931A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1982 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Jun 28, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/914
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P.sup.+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N.sup.+ region through the third window. The P-N junction between the N.sup.+ region and the deep P.sup.+ base region terminates at the surface of the wafer. The second oxide layer is removed, exposing the P-N junction, and the wafer i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.