Self-aligned oxide isolated process and device
US4443932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 1982 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Jan 18, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Improved self-aligned semiconductor devices are made using two sets of superposed pattern forming layers; a master mask layer set containing the self-aligned patterns, and a pattern selector layer set which allows different apertures in the master mask layer to be selectively re-opened so that different device regions may be sequentially formed. The master mask layer is a double layer of a first material resistant to typical device forming processes, covered by a second etch stop material. The selector layer may be a single process resistant material or a double layer. Using combinations of silicon oxide and nitride, the process is applied to the formation of silicon islands with emitters and emitter, base, and collector contacts self-aligned to each other and a surrounding oxide isolation region. Significant area and cost savings are achieved without additional masking steps or precision alignments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.