Transistorized focal plane having floating gate output nodes
US4445117A · kind A · utility
21Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1981 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Dec 28, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A transistorized monolithic focal plane array is formed on a semiconductive substrate and comprises a plurality of detectors associated with a corresponding plurality of source follower or inverter transistors. The array is row addressable. The gate of the source follower transistor comprises a floating node which is charged by the corresponding detector in proportion to the incident photon flux, the gate being periodically reset. The invention combines the advantages of compactness and low capacitance of charge coupled device imagers and low noise characteristics of prior art imagers comprising discrete transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.