Data steering logic for the output of a cache memory having an odd/even bank structure
US4445172A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1980 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Dec 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.