Memory protection circuit for an electronic postage meter
US4445198A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1981 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Sep 29, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic postage meter includes a memory protection circuit. The memory protection circuit prevents the inadvertent writing of spurious data into memory locations in the nonvolatile memory during a power down cycle. The memory protection circuit works in conjection with a WRITE voltage terminal associated with the nonvolatile memory. Means couple a first voltage source providing a predetermined polarity voltage to the WRITE voltage terminal when a predetermined power condition exists such that the nonvolatile memory is enabled to have data written into memory locations. When the predetermined power condition does not exist, the means utilize a second different voltage source to change the voltage level at the WRITE voltage terminal to insure that data is not written into the memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.