Memory device
US4445204A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1981 |
| Grant date | Apr 24, 1984 |
| Priority date | — |
| Expiry date | Oct 5, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device provided with an improved control circuit for enabling effective interface with a CPU. The device comprises a memory circuit, a first terminal for receiving a strobe signal for placing the memory circuit in an accessed state, a second terminal for receiving a chain of clock signals, digital counter for counting the clock signals in response to the strobe signal having a plurality of different value of count, output terminals, a circuit for selectively deriving a count signal from one of the count output terminal according to a programmed state, and a ready signal generating circuit for generating a ready signal for indicating the completion of the access operation of the memory circuit in response to the count signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.